This invention relates to the field of data acquisition, and more particularly to the field of data acquisition in a logic analyzer with an acquisition memory that is partitioned into a number of acquisition memory sections.
Logic analyzers are digital data acquisition instruments that allow a user to acquire and analyze digital data from a large number of logic signals, such as the address, data, and control lines of a microprocessor. The logic analyzer periodically compares each of these logic signals to a reference threshold in order to determine which logic state, high or low, each of the lines is in.
Trigger sections, or trigger machines, allow the user to specify when in time he or she would like to acquire data, i.e., which data they are interested in. Even the largest memories for data storage are quickly filled by all of the data occurring in a fast electronic system, so the process of deciding which data to store is very important. The data from a system under test is typically sent to a circular memory. This memory can be repeatedly overwritten and refilled many times with useless information before the interval of interest is reached.
When the triggering conditions have been satisfied, the flow of new data into the circular memory is interrupted and the data already in the memory is saved. This can occur immediately upon the occurrence of the trigger condition, and the contents of the memory will then reflect entirely the activity that occurred prior to the trigger event, i.e., will be "pretrigger" data. Conversely, if the memory is allowed to keep filling for its whole length after the trigger condition occurs, the contents of the memory will reflect entirely the activity that occurred immediately after the trigger event, i.e., will be "posttrigger" data. Typically, any one of a number of combinations of pretrigger and posttrigger data can be selected by a choice of trigger position. Which combination a user chooses will be dictated by the problem they are trying to solve and which conditions in the temporal vicinity of the problem can be identified well enough to program the trigger machine.
U.S. Pat. No. 4,654,848 to Kazuo Noguchi for a "Multi-Trigger Logic Analyzer" discloses a logic analyzer capable of generating multiple triggers to perform multiple data acquisitions. To accommodate the data from these multiple acquisitions, the acquisition memory of this logic analyzer is partitioned into a number of smaller data acquisition memory sections. The trigger machine of this logic analyzer is capable of changing word recognizer values during operation so that each of the multiple triggers that it produces can be in response to a different data pattern. This allows each portion of memory to be used for distinct and non-repetitive acquisitions.
Partitioned acquisition memory can also be used to make multiple data acquisitions using the same trigger criteria. For example, one might wish to repeatedly acquire the data in the vicinity of a particular recurring event to look for differences that appear in that data. However, for some types of problems, a view of the activity surrounding the first N trigger events does not help to solve the operator's problem. For certain classes of problems, the user of a logic analyzer would prefer to be able to examine data surrounding the last N trigger events before that trigger event ceases to occur for some unknown reason.
For example, a computer obtaining successive blocks of data from a disk drive crashes intermittently in a way that suggests that something in the data may provide a clue to the crashes. So, the operator would like to be able to examine the data and other activity in the vicinity of the last several data block requests. A trigger condition can be defined that will cause a trigger to occur each time a data block request occurs. Then, when the operator notices that the system under test is no longer producing the triggering event, he would like to be able to view the activity that occurred in the vicinity of the last occurrence of that trigger event, and the several immediately preceding it, to try to figure out what is causing the crashes.
Some logic analyzers have a reference memory, or multiple reference memories, as well as an acquisition memory, thus permitting one set of acquired data to be saved while another set is acquired. Using a logic analyzer with a single reference memory, one can make repeated acquisitions and copy the contents of the acquisition memory to the reference memory between each one of them. This gives a view of the data in the vicinity of the last occurrence of the trigger event, but no information about the data in the vicinity of the second to last or third to last triggers. If the logic analyzer has multiple reference memories, it can store the data associated with more than one trigger, but, because it takes considerable time to transfer the data between memories, there will always be gaps in time during which any number of additional triggers may have occurred without the associated data being captured.
What is desired is a method that will permit a logic analyzer to store the activity around the last in a series of triggering events while also storing the activity around several other triggering events immediately preceding the last trigger.